View DS3070W-100_4794962.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the ds3070w consists of a static ram, a nonvolatile (nv) controller, a year 2000-compliant real-time clock (rtc), and an internal rechargeable manganese lithium (ml) battery. these components are encased in a sur- face-mount module with a 256-ball bga footprint. whenever v cc is applied to the module, it recharges the ml battery, powers the clock and sram from the external power source, and allows the contents of the clock registers or sram to be modified. when v cc is powered down or out-of-tolerance, the controller write- protects the memory contents and powers the clock and sram from the battery. the ds3070w also con- tains a power-supply monitor output ( rst ), as well as a user-programmable interrupt output ( irq /ft). applications raid systems and servers gaming pos terminals fire alarms industrial controllers plcs data-acquisition systems routers/switches features single-piece, reflowable, 27mm x 27mm bga package footprint internal manganese lithium battery and charger integrated real-time clock unconditionally write-protects the clock and sram when v cc is out-of-tolerance automatically switches to battery supply when v cc power failures occur reset output can be used as a cpu supervisor interrupt output can be used as a cpu watchdog timer industrial temperature range (-40? to +85?) ul recognized ds3070w 3.3v single-piece 16mb nonvolatile sram with clock ______________________________________________ maxim integrated products 1 ce data address int rst a0?0 dq0? ce 21 bits 8 bits microprocessor or dsp ds3070w 2048k x 8 nv sram and rtc wr we rd oe int irq/ft cs cs typical operating circuit rev 1; 10/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information pin configuration appears at end of data sheet. part temp range pin-package speed supply voltage DS3070W-100# -40? to +85? 256-ball 27mm x 27mm bga module 100ns 3.3v ?.3v # denotes a rohs-compliant device that may include lead that is exempt under the rohs requirements.
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on any pin relative to ground......-0.3v to +4.6v operating temperature range ...........................-40? to +85? storage temperature range ...............................-40? to +85? soldering temperature range..........see ipc/jedec j-std-020 parameter symbol conditions min typ max units supply voltage v cc 3.0 3.3 3.6 v input logic 1 v ih 2.2 v cc v input logic 0 v il 0.0 0.4 v pin capacitance (t a = +25 c.) parameter symbol conditions min typ max units input capacitance c in not production tested 15 pf input/output capacitance c out not production tested 15 pf dc electrical characteristics (v cc = 3.3v 0.3v, t a = -40 c to +85 c.) parameter symbol conditions min typ max units input leakage current i il -1.0 +1.0 a i/o leakage current i io ce = cs = v cc -1.0 +1.0 a output-current high i oh at 2.4v -1.0 ma output-current low i ol at 0.4v 2.0 ma output-current low rst rst at 0.4v (note 1) 8.0 ma output-current low irq /ft i ol irq /ft at 0.4v (note 1) 7.0 ma i ccs1 ce = cs = 2.2v 0.5 7 standby current i ccs2 ce = cs = v cc - 0.2v 0.2 5 ma operating current i cco1 t rc = 200ns, outputs open 50 ma write protection voltage v tp 2.8 2.9 3.0 v
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock _____________________________________________________________________ 3 ac electrical characteristics (v cc = 3.3v 0.3v, t a = -40 c to +85 c.) DS3070W-100 parameter symbol conditions min max units read cycle time t rc 100 ns access time t acc 100 ns oe to output valid t oe 50 ns rtc oe to output valid t oec 60 ns ce or cs to output valid t co 100 ns oe or ce or cs to output active t coe (note 2) 5 ns output high impedance from deselection t od (note 2) 40 ns output hold from address t oh 5ns write cycle time t wc 100 ns write pulse width t wp (note 3) 75 ns address setup time t aw 0ns t wr1 (note 4) 5 write recovery time t wr2 (note 5) 20 ns output high impedance from we t odw (note 2) 40 ns output active from we t oew (note 2) 5 ns data setup time t ds (note 6) 40 ns t dh1 (note 4) 0 data hold time t dh2 (note 5) 20 ns chip-to-chip setup time t ccs 40 ns power-down/power-up timing (t a = -40 c to +85 c.) parameter symbol conditions min typ max units v cc fail detect to ce , cs , and we inactive t pd (note 7) 1.5 s v cc slew from v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce , cs , and we inactive t pu 2ms v cc valid to end of write protection t rec 125 ms v cc fail detect to rst active t rpd (note 1) 3.0 s v cc valid to rst inactive t rpu (note 1) 40 350 525 ms
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock 4 _____________________________________________________________________ note 1: irq /ft and rst are open-drain outputs and cannot source current. external pullup resistors should be connected to these pins to realize a logic-high level. note 2: these parameters are sampled with a 5pf load and are not 100% tested. note 3: t wp is specified as the logical and of ce with we for sram writes, or cs with we for rtc writes. t wp is measured from the latter of the two related edges going low to the earlier of the two related edges going high. note 4: t wr1 and t dh1 are measured from we going high. note 5: t wr2 and t dh2 are measured from ce going high for sram writes or cs going high for rtc writes. note 6: t ds is measured from the earlier of ce or we going high for sram writes, or from the earlier of cs or we going high for rtc writes. note 7: in a power-down condition, the voltage on any pin may not exceed the voltage on v cc . note 8: the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. minimum expected data-retention time is based upon a maximum of two +230 c convection reflow exposures, fol- lowed by a fully charged cell. full charge occurs with the initial application of v cc for a minimum of 96 hours. this parame- ter is assured by component selection, process control, and design. it is not measured directly during production testing. note 9: we is high for any read cycle. note 10: oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high-impedance state. note 11: if the ce or cs low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high-impedance state during this period. note 12: if the ce or cs high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high-impedance state during this period. note 13: if we is low or the we low transition occurs prior to or simultaneously with the related ce or cs low transition, the output buffers remain in a high-impedance state during this period. data retention (t a = +25 c.) parameter symbol conditions min typ max units expected data-retention time (per charge) t dr (notes 7, 8) 2 3 years ac test conditions input pulse levels: v il = 0.0v, v ih = 2.7v input pulse rise and fall times: 5ns input and output timing reference level: 1.5v output load: 1 ttl gate + c l (100pf) including scope and jig
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock _____________________________________________________________________ 5 read cycle output data valid t rc t acc t co t oe t oec t oh t od t od t coe t coe v ih v ih v il v oh v ol v oh v ol v il v ih addresses ce or cs oe d out (see note 9.) v ih v ih v ih v ih v il v il v il
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock 6 _____________________________________________________________________ write cycle 1 data in stable addresses we d out d in t wc v ih v ih v ih v ih v il v il v il high impedance v ih v ih v il v il v ih v il v il v il v il t aw t wp t oew t dh1 t ds t odw t wr1 (see notes 2, 3, 4, 6, 10 13.) ce or cs write cycle 2 t wc t aw t dh2 t ds t coe t odw t wp t wr2 v ih v il v ih addresses we d out d in v il v ih v il v ih v il v il v il v il v ih v ih v il v ih data in stable v il v ih v il (see notes 2, 3, 5, 6, 10 13.) ce or cs
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock _____________________________________________________________________ 7 power-down/power-up condition t dr t pu t f t pd t rpu t rpd slews with v cc t r v ol v ih v ol t rec v cc v tp ~ 2.5v ce, we rst backup current supplied from lithium battery (see notes 1, 7.) and cs typical operating characteristics (v cc = 3.3v, t a = +25 c, unless otherwise noted.) 0 4 2 8 6 10 12 supply current vs. operating frequency ds3070w toc01 v cc (v) supply current (ma) 3.0 3.2 3.3 3.1 3.4 3.5 3.6 t a = +25 c 1mhz ce-activated 50% duty cycle 1mhz address- activated 100% duty cycle 5mhz address- activated 100% duty cycle 5mhz ce-activated 50% duty cycle 500 600 800 700 900 1000 3.0 3.2 3.1 3.3 3.4 3.5 3.6 supply current vs. supply voltage ds3070w toc02 v cc (v) supply current ( a) v cc = ce = 3.3v, v bat = v charge , osc = on 0 1 2 3 4 5 6 7 8 0 0.2 0.4 0.6 0.8 1.0 battery charger current vs. battery voltage delta v below v charge (v) battery charger current, i charge (ma) v cc = ce = 3.3v v charge ds3070w toc03
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock 8 _____________________________________________________________________ 1.0 0.5 0 -0.5 -1.0 -40 10 -15 35 60 85 v charge percent change vs. temperature ds3070w toc04 temperature ( c) v charge percent change from 25 c (%) v cc = 3.3v, v bat = v charge 3.00 2.95 2.90 2.85 2.80 -40 10 -15 35 60 85 v tp vs. temperature ds3070w toc05 temperature ( c) write protect, v tp (v) 2.5 2.7 3.1 2.9 3.3 3.5 -5 -3 -4 -2 -1 0 dq v oh vs. dq i oh ds3070w toc06 i oh (ma) v oh (v) v cc = 3.3v 0.4 0.3 0.2 0.1 0 02 1 345 dq v ol vs. dq i ol ds3070w toc07 i ol (ma) v ol (v) v cc = 3.3v 0 0.2 0.1 0.4 0.3 0.5 0.6 010 51520 irq/ft output voltage low vs. output current low ds3070w toc08 i ol (ma) v ol (v) v cc = 3.3v 0 0.2 0.1 0.4 0.3 0.5 0.6 010 51520 ds3070w toc09 i ol (ma) v ol (v) rst output voltage low vs. output current low v cc = 2.8v 0 1.0 0.5 2.0 1.5 2.5 3.0 3.5 4.0 0 1.0 1.5 0.5 2.0 2.5 3.0 3.5 4.0 ds3070w toc10 v cc power-up (v) rst voltage vs. v cc during power-up rst voltage with pullup resistor (v) t a = +25 c typical operating characteristics (continued) (v cc = 3.3v, t a = +25 c, unless otherwise noted.)
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock _____________________________________________________________________ 9 pin description balls name description a1, a2, a3, a4 gnd ground b1, b2, b3, b4 irq /ft interrupt/frequency test output c1, c2, c3, c4 a15 address input 15 d1, d2, d3, d4 a16 address input 16 e1, e2, e3, e4 rst reset output f1, f2, f3, f4 v cc supply voltage g1, g2, g3, g4 we write enable input h1, h2, h3, h4 oe output enable input j1, j2, j3, j4 ce sram chip enable input k1, k2, k3, k4 dq7 data input/output 7 l1, l2, l3, l4 dq6 data input/output 6 m1, m2, m3, m4 dq5 data input/output 5 n1, n2, n3, n4 dq4 data input/output 4 p1, p2, p3, p4 dq3 data input/output 3 r1, r2, r3, r4 dq2 data input/output 2 t1, t2, t3, t4 dq1 data input/output 1 u1, u2, u3, u4 dq0 data input/output 0 v1, v2, v3, v4 gnd ground w1, w2, w3, w4 gnd ground y1, y2, y3, y4 gnd ground a17, a18, a19, a20 gnd ground b17, b18, b19, b20 a18 address input 18 c17,c18,c19, c20 a17 address input 17 d17, d18, d19, d20 a14 address input 14 e17, e18, e19, e20 a13 address input 13 f17, f18, f19, f20 a12 address input 12 g17, g18, g19, g20 a11 address input 11 h17, h18, h19, h20 a10 address input 10 j17, j18, j19, j20 a9 address input 9 k17, k18, k19, k20 a8 address input 8 l17, l18, l19, l20 a7 address input 7 m17, m18, m19, m20 a6 address input 6 balls name description n17, n18, n19, n20 a5 address input 5 p17, p18, p19, p20 a4 address input 4 r17, r18, r19, r20 a3 address input 3 t17, t18, t19, t20 a2 address input 2 u17, u18, u19, u20 a1 address input 1 v17, v18, v19, v20 a0 address input 0 w17, w18, w19, w20 gnd ground y17, y18, y19, y20 gnd ground a5, b5, c5, d5 n.c. no connection a6, b6, c6, d6 n.c. no connection a7, b7, c7, d7 n.c. no connection a8, b8, c8, d8 n.c. no connection a9, b9, c9, d9 n.c. no connection a10, b10, c10, d10 v cc supply voltage a11, b11, c11, d11 n.c. no connection a12, b12, c12, d12 n.c. no connection a13, b13, c13, d13 n.c. no connection a14, b14, c14, d14 n.c. no connection a15, b15, c15, d15 a19 address input 19 a16, b16, c16, d16 a20 address input 20 u5, v5, w5, y5 cs rtc chip select input u6, v6, w6, y6 n.c. no connection u7, v7, w7, y7 n.c. no connection u8, v8, w8, y8 n.c. no connection u9, v9, w9, y9 n.c. no connection u10, v10, w10, y10 n.c. no connection u11, v11, w11, y11 n.c. no connection u12, v12, w12, y12 n.c. no connection u13, v13, w13, y13 n.c. no connection u14, v14, w14, y14 n.c. no connection u15, v15, w15, y15 n.c. no connection u16, v16, w16, y16 n.c. no connection
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock 10 ____________________________________________________________________ functional diagram current-limiting resistor battery-charging/shorting protection circuitry (u.l. recognized) redundant logic delay timing circuitry charger current-limiting resistor v tp ref v sw ref gnd ml ce rst ce redundant series fet sram dq0 7 oe we v cc v cc uninterrupted power supply for the sram and rtc irq/ft ds3070w oe we a0 a20 a0-a3 real-time clock 32.768khz we oe cs cs
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock ____________________________________________________________________ 11 detailed description the ds3070w is a 16mb (2048k x 8 bits) fully static, nv memory similar in function and organization to the ds1270w nv sram, but also containing an rtc and rechargeable ml battery. the ds3070w nv sram con- stantly monitors v cc for an out-of-tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. there is no limit to the number of write cycles that can be exe- cuted, and no additional support circuitry is required for microprocessor interfacing. this device can be used in place of sram, eeprom, or flash components. user access to either the sram or the real-time clock registers is accomplished with a byte-wide interface and discrete control inputs, allowing for a direct inter- face to many 3.3v microprocessor devices. the ds3070w rtc contains a full-function, year 2000- compliant (y2kc) clock/calendar with an rtc alarm, watchdog timer, battery monitor, and power monitor. rtc registers contain century, year, month, date, day, hours, minutes, and seconds data in a 24-hour bcd format. corrections for day of the month and leap year are made automatically. the ds3070w rtc registers are double-buffered into an internal and external set. the user has direct access to the external set. clock/calendar updates to the exter- nal set of registers can be disabled and enabled to allow the user to access static data. assuming the internal oscillator is on, the internal registers are contin- ually updated, regardless of the state of the external registers, assuring that accurate rtc information is always maintained. the ds3070w contains interrupt ( irq /ft) and reset ( rst ) outputs, which can be used to control cpu activ- ity. the irq /ft interrupt output can be used to gener- ate an external interrupt when the rtc register values match user-programmed alarm values. the interrupt is always available while the device is powered from the system supply, and it can be programmed to occur when in the battery-backed state to serve as a system wake-up. the irq /ft output can also be used as a cpu watchdog timer. cpu activity is monitored and an interrupt can be activated if the correct activity is not detected. the rst output can be used to detect a sys- tem power-down or failure and hold the cpu in a safe state until normal power returns. the ds3070w constantly monitors the voltage of the internal battery. the battery-low flag (blf) in the rtc flags register is not writeable and should always be a 0 when read. should a 1 ever be present, the battery voltage is below 2v and the contents of the clock and sram are questionable. the ds3070w module is constructed on a standard 256- ball, 27mm x 27mm bga substrate. unlike other sur- face-mount nv memory modules that require the battery to be removable for soldering, the internal ml battery can tolerate exposure to convection reflow soldering temperatures, allowing this single-piece component to be handled with standard bga assembly techniques. table 1. rtc/memory operational truth table cs we ce oe mode icc outputs 0 1 1 0 rtc read active active 0 1 1 1 rtc read active high impedance 0 0 1 x rtc write active high impedance 1 1 0 0 sram read active active 1 1 0 1 sram read active high impedance 1 0 0 x sram write active high impedance 1 x 1 x standby standby high impedance 0 x 0 x invalid (1) active invalid x = don? care. (1) = see figure 4.
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock 12 ____________________________________________________________________ sram read mode the ds3070w executes an sram read cycle whenever cs (rtc chip select) and we (write enable) are inactive (high) and ce (sram chip enable) is active (low). the unique address specified by the 21 address inputs (a0 to a20) defines which of the 2,097,152 bytes of sram data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if ce and oe access times are not satisfied, then data access must be measured from the later occurring sig- nal ( ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. sram write mode the ds3070w executes an sram write cycle whenever cs is inactive (high) and the ce and we signals are active (low) after address inputs are stable. the later- occurring falling edge of ce or we determines the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the cs and oe control signal should be kept inactive (high) during sram write cycles to avoid bus contention. however, if the output dri- vers have been enabled ( ce and oe active) then we dis- ables the outputs in t odw from its falling edge. data address b7 b6 b5 b4 b3 b2 b1 b0 function/range xxxxfh 10 year year year 00 99 xxxxeh x x x 10 m month month 01 12 xxxxdh x x 10 date date date 01 31 xxxxch x ft x x x day day 01 07 xxxxbh x x 10 hour hour hour 00 23 xxxxah x 10 minutes minutes minutes 00 59 xxxx9h osc 10 seconds seconds seconds 00 59 xxxx8h w r 10 century century control 00 39 xxxx7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog ? xxxx6h ae y abe y y y y y interrupts ? xxxx5h am4 y 10 date date alarm date 01 31 xxxx4h am3 y 10 hours hours alarm hours 00 23 xxxx3h am2 10 minutes minutes alarm minutes 00 59 xxxx2h am1 10 seconds seconds alarm seconds 00 59 xxxx1h y y y y y y y y unused ? xxxx0h wf af 0 blf 0 0 0 0 flags ? x = don? care address bits. x = unused. read/writeable under write and read bit control. ft = frequency test bit. osc = oscillator start/stop bit. w = write bit. r = read bit. wds = watchdog steering bit. bmb0?mb4 = watchdog multiplier bits. rb0, rb1 = watchdog resolution bits. ae = alarm flag enable. y = unused. read/writeable without write and read bit control. abe = alarm in backup mode enable. am1?m4 = alarm mask bits. wf = watchdog flag. af = alarm flag. 0 = reads as a 0 and cannot be changed. blf = battery low flag. clock operations table 2. rtc register map
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock ____________________________________________________________________ 13 rtc read mode the ds3070w executes an rtc read cycle whenever ce (sram chip enable) and we (write enable) are inactive (high) and cs (rtc chip select) is active (low). the least significant 4 address inputs (a0 to a3) define which of the 16 rtc registers is to be accessed (see table 2). valid data is available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that cs and oe (output enable) access times are also satisfied. if cs and oe access times are not satisfied, then data access must be measured from the later occurring signal ( cs or oe ) and the limiting parameter is either t co for cs or t oec for oe rather than address access. rtc write mode the ds3070w executes an rtc write cycle whenever ce is inactive (high) and the cs and we signals are active (low) after address inputs are stable. the later- occurring falling edge of cs or we determines the start of the write cycle. the write cycle is terminated by the earlier rising edge of cs or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the ce and oe control signals should be kept inactive (high) during rtc write cycles to avoid bus contention. however, if the out- put drivers have been enabled ( cs and oe active) then we disables the outputs in t odw from its falling edge. clock oscillator mode the oscillator can be turned off to minimize battery cur- rent drain. the osc bit is the msb of the seconds register, and must be initialized to a 0 to start the oscil- lator upon first power application. the osc bit is facto- ry set to a 1 prior to shipment. oscillator operation and frequency can be verified by setting the ft bit to a 1 and monitoring the irq /ft output for 512hz. reading the clock when reading the rtc data, it is recommended to halt updates to the external set of double-buffered rtc reg- isters. this puts the external registers into a static state, allowing the data to be read without register values changing during the read process. normal updates to the internal registers continue while in this state. external updates are halted by writing a 1 to the read bit (r). as long as a 1 remains in the r bit, updating is inhibited. after a halt is issued, the registers reflect the rtc count (day, date, and time) that was current at the moment the halt command was issued. normal updates to the external set of registers resume within 1 second after the r bit is set to a 0 for a minimum of 500s. the r bit must be a 0 for a minimum of 500s to ensure the external registers have fully updated. setting the clock as with a clock read, it is also recommended to halt updates prior to setting new time values. setting the write bit (w) to a 1 halts updates of the external rtc registers 8h to fh. after setting the w bit to a 1, the rtc registers can be loaded with the desired count (day, date, and time) in bcd format. setting the w bit to a 0 then transfers the values written to the internal registers and allows normal clock operation to resume. frequency test mode the ds3070w frequency test mode uses the irq /ft open-drain output. with the oscillator running, the irq /ft output toggles at 512hz when the ft bit is a 1, the alarm-flag enable bit (ae) is a 0, and the watchdog- enable bit (wds) is a 1 or the watchdog register is written to 00h (ft ? ae ? (wds + watchdog )). the irq /ft output and the frequency test mode can be used to measure the actual frequency of the 32.768khz rtc oscillator. the ft bit is reset to a 0 on power-up. using the clock alarm the alarm settings and control for the ds3070w reside within rtc registers 2h 5h. the interrupts register (6h) contains two alarm-enable bits: alarm enable (ae) and alarm in backup enable (abe). the ae and abe bits must be set as described below for the irq /ft out- put to be activated when an alarm match occurs. the alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. it can also be programmed to go off while the ds3070w is in the data retention mode to serve as a system wake-up. alarm mask bits am1 to am4 control the alarm mode (see table 3). configurations not listed in the table will default to the once-per-second mode to notify the user of an incorrect alarm setting.
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock 14 ____________________________________________________________________ when the rtc register values match alarm register set- tings, the alarm flag (af) is set to a 1. if ae is also a 1, the alarm condition activates the irq /ft output. when cs is active, the irq /ft signal can be cleared by hold- ing the flags register address stable for t rc and forc- ing either oe or we active (see figure 1). the flag does not change state until the end of the read/write cycle and after the irq /ft signal has deasserted. to avoid inadvertently clearing the irq /ft signal while preparing for subsequent write/read cycles at other register addresses, assure that t aw is met for that subsequent address (see figure 2). the irq /ft output can also be activated during battery backup mode. the irq /ft goes low if an alarm occurs and both ae and abe are set to 1. the ae and abe bits are reset to 0 during the power-up transition, but an alarm generated during power-up will set af to a 1. therefore, the af bit can be read after system power- up to determine if an alarm was generated during the power-up sequence. figure 3 illustrates alarm timing during battery backup mode and power-up states. table 3. alarm mask bits am4 am3 am2 am1 alarm rate 1 1 1 1 once per second 1 1 1 0 when seconds match 1 1 0 0 when minutes and seconds match 1 0 0 0 when hours, minutes, and seconds match 0 0 0 0 when date, hours, minutes, and seconds match ce we or oe cs a0 a3 irq/ft t rc max address 0h high impedance figure 1. clearing active irq waveforms
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock ____________________________________________________________________ 15 ce we or oe cs a0 a3 irq/ft t as address 0h address xh high impedance intentional write or read at address xh inadvertent write or read of rtc flags register will reset irq/ft figure 2. prevent accidental clearing of irq waveforms v cc v tp high impedance high impedance abe, ae af irq/ft figure 3. battery back-up mode alarm waveforms
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock 16 ____________________________________________________________________ using the watchdog timer the watchdog timer can be used to detect an out-of- control processor. the user programs the watchdog timer by setting the desired timeout delay into the watchdog register. the five high-order watchdog register bits store a binary multiplier and the two lower- order watchdog bits select the resolution, where 00 = 1 / 16 second, 01 = 1 / 4 second, 10 = 1 second, and 11 = 4 seconds. the watchdog timeout value is then determined by multiplication of the 5-bit multiplier value with the 2-bit resolution value. (for example: writing 00001110 (0eh) into the watchdog register = 3 x 1 second, or 3 seconds.) if the processor does not reset the timer within the specified period, the watchdog flag (wf) is set to a 1 and a processor interrupt is generat- ed and stays active until either wf is read or the watchdog register is read or written. the msb of the watchdog register is the watchdog steering bit (wds). when wds is set to a 0, the watch- dog activates the irq /ft output when the watchdog times out. wds should not be written to a 1, and should be initialized to a 0 if the watchdog function is enabled. the watchdog timer resets when the processor per- forms a read or write of the watchdog register. the timeout period then starts over. the watchdog timer is disabled by writing a value of 00h to the watchdog register. the watchdog function is automatically dis- abled upon power-up and the watchdog register is cleared to 00h. clock accuracy the ds3070w modules are trimmed at the factory to an accuracy of 1 minute per month at +25 c. power-on default states upon each application of power to the device, the fol- lowing register bits are automatically set to 0: wds = 0, bmb0 bmb4 = 0, rb0 = 0, rb1 = 0, ae = 0, abe = 0. all other rtc bits are undefined. data-retention mode the ds3070w provides full functional capability for v cc greater than 3.0v and write-protects by 2.8v. data is maintained in the absence of v cc without additional support circuitry. the nv sram constantly monitors v cc . should the supply voltage decay, the nv sram automatically write-protects itself. all inputs become don t care, and all data outputs become high imped- ance. as v cc falls below approximately 2.5v (v sw ), the power-switching circuit connects the lithium energy source to the clock and sram to maintain time and retain data. during power-up, when v cc rises above v sw , the power-switching circuit connects external v cc to the clock and sram, and disconnects the lithium energy source. normal clock or sram operation can resume after v cc exceeds v tp for a minimum duration of t rec . battery charging when v cc is greater than v tp an internal regulator will charge the battery. the ul-approved charger circuit includes short-circuit protection and a temperature-sta- bilized voltage reference for on-demand charging of the internal battery. typical data retention expectations greater than 2 years per charge cycle are achievable. a maximum of 96 hours of charging time is required to fully charge a depleted battery. system power monitoring when the external v cc supply falls below the selected out-of-tolerance trip point, the output rst is forced active (low). once active, the rst is held active until the v cc supply has fallen below that of the internal bat- tery. on power-up, the rst output is held active until the external supply is greater than the selected trip point and one reset timeout period (t rpu ) has elapsed. this is sufficiently longer than t rec to ensure that the rtc and sram are ready for access by the micro- processor. freshness seal and shipping the ds3070w is shipped from dallas semiconductor with the rtc oscillator disabled and the lithium battery electrically disconnected, guaranteeing that no battery capacity has been consumed during transit or storage. as shipped, the lithium battery is ~60% charged, and no pre-assembly charging operations should be attempted. when v cc is first applied at a level greater than v tp , the lithium battery is enabled for backup operation. the user is required to enable the oscillator (msb of sec- onds register) and initialize the required rtc registers for proper timekeeping operation. a 96 hour initial bat- tery charge time is recommended for new system installations. applications information power-supply decoupling to achieve the best results when using the ds3070w, assure that all v cc and gnd balls are connected and decouple the power supply with a 0.1f capacitor. use a high-quality, ceramic surface-mount capacitor if possible.
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock ____________________________________________________________________ 17 surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. avoiding data bus contention care should be taken to avoid simultaneous access of the sram and rtc devices (see figure 4). any chip- enable overlap violates t ccs and can result in invalid and unpredictable behavior. using the open-drain irq /ft and rst outputs the irq /ft and rst outputs are open drain, and there- fore require pullup resistors to realize a high logic out- put level. pullup resistor values between 1k ? and 10k ? are typical. battery charging/lifetime the ds3070w charges an ml battery to maximum capacity in approximately 96 hours of operation when v cc is greater than v tp . once the battery is charged, its lifetime depends primarily on the v cc duty cycle. the ds3070w can maintain data from a single, initial charge for up to 2 years. once recharged, this deep- discharge cycle can be repeated for up to 20 times, producing a worst-case service life of 40 years. more typical duty cycles are of shorter duration, enabling the ds3070w to be charged hundreds of times, and extending the service life well beyond 40 years. recommended cleaning procedures the ds3070w can be cleaned using aqueous-based cleaning solutions. no special precautions are needed when cleaning boards containing a ds3070w module. removal of the topside label violates the environmental integrity of the package and voids the warranty of the product. t ccs t ccs ce v ih v ih v ih v ih cs figure 4. sram/rtc data bus control recommended reflow temperature profile profile feature sn-pb eutectic assembly average ramp-up rate (t l to t p ) 3 c/second max preheat - temperature min (t smin ) - temperature max (t smax ) - time (min to max) (ts) 100 c 150 c 60 to 120 seconds t smax to t l - ramp-up rate time maintained above: - temperature (t l ) - time (t l ) 183 c 60 to 150 seconds peak temperature (t p ) 225 +0/-5 c time within 5 c of actual peak temperature (t p ) 10 to 30 seconds ramp-down rate 6 c/second max time 25 c to peak temperature 6 minutes max note: all temperatures refer to topside of the package, mea- sured on the package body surface.
ds3070w 3.3v single-piece 16mb nonvolatile sram with clock maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. ds3070w bga modules are recognized by underwriters laboratory (ul) under file e99151. pin configuration a 12 34 789 0 5 6 7 8 90 1 2 34 56 1 2 34 1 1 1 2 5 678 9 1 1 1 1 1 1 1 11 1 2 1 1 1 11 1 1 7 8 9 0 0 1 2 3 4 5 6 ds3070w b c d e f g h j k l m n p r t u v w y a b c d e f g h j k l m n p r t u v w y top view gnd irq/ft a15 a16 rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd gnd gnd gnd a18 a17 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 gnd gnd cs n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. v cc n.c. n.c. n.c. n.c. a19 a20 springer package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . revision history pages changed at rev1: 1, 3, 4,18

▲Up To Search▲

Price & Availability of DS3070W-100

	To Download DS3070W-100 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .